Delta-sigma (ΔΣ) ADCs are widely used for high-fidelity conversion of analog signals into digital form. ΔΣ ADCs can be broadly classified as either discrete-time or continuous-time. Discrete-time ΔΣ ADCs are more common, owing to the high degree of precision that is possible in their implementation. On the other hand, continuous-time ΔΣ ADCs have the advantages of inherent anti-aliasing and high speed. This invention addresses one of the practical problems that leads to non-ideal performance in a high-speed continuous-time ΔΣ ADC: imperfect synchronization or timing between the sampling operation and the DAC update time. In a continuous-time ΔΣ ADC the output of the analog loop filter is sampled, (optionally) processed in discrete-time with more analog circuitry, and then converted into digital form. The digital output is fed back via one or more DACs into the loop filter. In order for this system to behave as desired, the time when feedback is applied or updated via the DACs must be well-controlled with respect to the time when the output of the loop filter is sampled. For bandpass systems, a timing error as small as 10% of a clock period can be problematic, and with a clock rate in the hundreds of MHz this translates into sub-ns timing-accuracy requirements. Achieving such accuracy is difficult, and requires careful design and layout, and possibly several loops through the design-layout-simulate cycle. In one approach, timing uncertainty is included in the NTF (noise transfer function) selection process, but this approach is overly restrictive and is not guaranteed to provide satisfactory results in all cases. In another approach, means for adjustment of the timing was included in the circuit, but no method for determining the required adjustment was described. So, while the need for synchronizing sampling and updating is known, there is no disclosure of how to automatically do it.